In order to drive scanning signal lines of a liquid crystal display device in particular, some scanning signal line drivers employ clock signals which are out of phase with each other so that their high level periods and/or low level periods do not overlap.
The clock signal, when it has a lower voltage than a power voltage of the scanning line driver, needs to be raised to the level of the power voltage. For this purpose, a level shifter circuit is widely used. In this connection, there has been developed a low-temperature polysilicon driver monolithic panel, in which pixels and drivers are monolithically formed on a single glass substrate.
The transistor characteristics (threshold voltage Vth, electron mobility μ) of transistors realized by such low-temperature polysilicon, however, are lower than those of a circuit, commonly known as an IC, formed on the silicon substrate. This is particularly notable in threshold voltage Vth.
Conventionally, such transistors are used to realize a level shifter circuit in the manner described below. As one conventional example, FIG. 21 shows a circuit diagram in which two kinds of clock signals having a lower voltage than the driving voltage are raised to the level of the driving voltage, and FIG. 22 shows a timing chart of such an operation.
FIG. 22 shows two kinds of clock signals CK1 and CK2. The clock signals CK1 and CK2 each have active high level periods and non-active low level periods. Further, the clock signals CK1 and CK2 are out of phase from each other so that their high level periods do not overlap.
Vdd0 is a potential difference between a high level voltage and a low level voltage of the clock signal, wherein the high level voltage of the clock signal is lower than the driving voltage. Vdd1 is a potential difference between a high level voltage and a low level voltage of output signals OUT1, OUT2, wherein the output signals OUT1 and OUT2 are obtained by raising the voltage levels of the clock signals CK1 and CK2 to the level of the driving voltage, respectively.
FIG. 21 shows a conventional level shifter circuit. The level shifter circuit has a first level shifter LS1 which varies the level of the clock signal CK1, and a second level shifter LS2 which varies the level of the clock signal CK2. Each of the first level shifter LS1 and the second level shifter LS2 is realized by an offsetter section 51 and a level shift section 52.
Each offsetter section 51 of the first level shifter LS1 and the second level shifter LS2 shown in FIG. 21 includes a constant current source transistor P1 and an N-channel MOS transistor N1 (“transistor N1” hereinafter), wherein the former is realized by a P-channel transistor.
The source and gate of the constant current source transistor P1 are connected to a driving power supply Vdd and a power supply Vss (low level of the clock signals CK1 and CK2), respectively. The drain of the constant current source transistor P1 is connected to the drain and gate of the transistor N1 and to the gate of an N-channel MOS transistor N2 of the level shift section 52. The source of the transistor N1 is connected to the power supply Vss.
Each level shift section 52 of the first level shifter LS1 and the second level shifter LS2 shown in FIG. 21 includes a constant current source transistor P2, the N-channel MOS transistor N2 (“transistor N2” hereinafter), and inverters I1 and I2, wherein the constant current source transistor P2 is realized by a P-channel MOS transistor.
The gate of the constant current source transistor P2 is connected to the power supply Vss. The drain of the constant current source transistor P2 is connected to the drain of the transistor N2 and to the input terminal of the inverter I1. The source of the constant current source transistor P2 is connected to a driving power supply Vdd.
The clock signals CK1 and CK2, whose voltage levels are lower than a voltage (driving voltage Vdd) of the driving power supply Vdd, are respectively supplied to the first level shifter LS1 and the second level shifter LS2 via the source of the transistors N2.
The output terminal of the inverter I1 is connected to the input terminal of the inverter I2, and the inverter I2 outputs the output signal OUT1 in the first level shifter LS1 and the output signal OUT2 in the second level shifter LS2.
The level shifter circuit operates as follows. In the first level shifter LS1 and the second level shifter LS2, the offsetter section 51 applies a level shift voltage to the gate of the transistor N2, the level shift voltage being an intermediate voltage of the driving voltage Vdd and the voltage of the power supply Vss (“power voltage Vss” hereinafter). The level shift voltage will be referred to as an offset voltage. Under a steady state, the offset voltage is slightly higher than a threshold voltage Vth of the transistor N1 or the threshold voltage Vth.
In the first level shifter LS1 and the second level shifter LS2, the constant current source transistor P2 of the level shift section 52 flows a constant current ia. The constant current ia flows into the junction of the drain of the constant current source transistor P2 and the input terminal of the inverter I1, which direction of current flow is denoted as positive.
In the first level shifter LS1 and the second level shifter LS2, the transistor N2 flows a current ib into the input terminal of the clock signals CK1, CK2, whose voltage levels are lower than the driving voltage Vdd. The direction of this current flow is denoted as positive. A current that flows into the inverter I1 from the junction of the drain of the constant current source transistor P2 and the input terminal of the inverter I1 is a current ic, which direction of current flow is denoted as positive.
The offset voltage from the offsetter section 51 is applied to the gate of the transistor N2, which has essentially the same characteristics as the transistor N1. Therefore, the voltage applied to the gate of the transistor N2 is slightly higher than the threshold voltage Vth of the transistor N2 or the threshold voltage Vth. The current flow through the transistor N2 may be controlled with respect to small changes in voltage level of the clock signal CK1, CK2 supplied to the source of the transistor N2.
When the clock signal CK1, CK2 is at low voltage level, the potential difference across the gate and source of the transistor N2 is slightly greater than the threshold voltage Vth of the transistor N2 or the threshold voltage Vth, and the transistor N2 conducts. Under a conducting state of the transistor N2, the current ia flows into the terminal of the clock signal CK1, CK2 that is supplied to the source of the transistor N2 (feedthrough current).
Here, the current ic, which flows into the inverter I1 from the junction of the drain of the constant current source transistor P2 and the input terminal of the inverter I1 (positive direction), becomes a pull current that flows into the terminal of the clock signal CK1 or CK2 that is supplied to the source of the transistor N2. Thus, the current ic is negative in this case.
As a result, the stored charge at the gate of a MOS transistor in the inverter I1 is released to cause a potential drop. When the voltage decreases below the theoretical inverting voltage of the inverter I1, the inverter I1 outputs the driving voltage Vdd to the input terminal of the inverter I2. As a result, the output signal OUT1, OUT2 of the inverter I2 becomes the power voltage Vss (low level of the clock signals CK1 and CK2).
On the other hand, when the clock signal CK1, CK2 is at high voltage level, the potential difference across the gate and source of the transistor N2 becomes smaller than the threshold voltage Vth of the transistor N2. As a result, the current ib through the transistor N2 is reduced to zero, or only a small amount of current ib flows therethrough, if any.
As a result, the constant current ia through the junction of the drain of the constant current source transistor P2 and the input terminal of the inverter I1 flows into the input terminal of the inverter I1 almost completely. Thus, in this case, the current ic is positive. In response, positive charges accumulate at the gate of the MOS transistor in the inverter I1, thereby increasing the gate voltage of the MOS transistor.
When the gate voltage of the MOS transistor exceeds the theoretical inverting voltage of the inverter I1, the inverter I1 outputs the power voltage Vss to the input terminal of the inverter I2. The inverter I2, in response, outputs the driving voltage Vdd.
In this manner, the high voltage level of the clock signal CK1, CK2, which is lower than the driving voltage Vdd, is raised to the level of the driving voltage Vdd, so as to generate the output voltage OUT1, OUT2.
The clock signals with the increased voltage levels may be used to operate the shift register, for example, as disclosed in Japanese Publication for Unexamined Patent Application No. 135093/2001 (Tokukai 2001-135093), so as to drive the scanning line driver of a liquid crystal display device.
The corresponding US application (U.S. Ser. No. 09/703,918; filed on Nov. 1, 2000) of the foregoing publication is incorporated herein as a reference.
As another related art of the present invention, Japanese Publication for Unexamined Patent Application No. 298445/1996 (Tokukaihei 8-298445; published on Nov. 12, 1996) is available. (Corresponding U.S. Pat. No. 5,841,317; Date of patent Nov. 24, 1998.)
In recent years, liquid crystal display devices have been widely used as display devices of small portable terminals or portable phones. In these applications, low power consumption is strongly desired in order to satisfy the portable functionality of these devices.
However, in the shift register of the foregoing publication using the level shifter circuit as described above, the level shifters, such as the first level shifter LS1 and the second level shifter LS2, making up the level shifter circuit operate by constantly supplying current to the transistors, including the constant current source transistor P1 and the transistor N1 of the offsetter section 51, and the constant current source transistor P2 and the transistor N2 of the level shift section 52.
In this case, the plurality of level shifters consumes power even when the clock signals are not required, i.e., when the clock signals are non-active. This prevents the power consumption of the level shifter circuit from being reduced, with the result that the power consumption of the liquid crystal display device is increased. Consequently, batteries or other power sources of the small portable terminals or portable phones run out quickly, reducing the operable hours of these devices.